The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 09, 2021

Filed:

Dec. 04, 2018
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Charles L Arvin, Poughkeepsie, NY (US);

Brian W Quinlan, Poughkeepsie, NY (US);

Steve Ostrander, Poughkeepsie, NY (US);

Thomas Weiss, Poughkeepsie, NY (US);

Mark W Kapfhammer, Poughkeepsie, NY (US);

Shidong Li, Poughkeepsie, NY (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/538 (2006.01); H01L 25/065 (2006.01); H01L 23/00 (2006.01); H01L 23/31 (2006.01); H01L 23/373 (2006.01); H01L 25/00 (2006.01); H01L 21/48 (2006.01); H01L 21/56 (2006.01);
U.S. Cl.
CPC ...
H01L 23/5381 (2013.01); H01L 21/4807 (2013.01); H01L 21/4853 (2013.01); H01L 21/563 (2013.01); H01L 23/3185 (2013.01); H01L 23/3731 (2013.01); H01L 24/16 (2013.01); H01L 24/81 (2013.01); H01L 25/0655 (2013.01); H01L 25/50 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/81132 (2013.01); H01L 2224/81815 (2013.01);
Abstract

A multiple chip carrier assembly including a carrier having a first surface and a second surface is attached to a plurality of chips is described. The plurality of chips include a first chip and a second chip. Each of the chips has first surface with a first set of solder balls for connecting to a package and a second set of solder balls for connecting to a high signal density bridge element. A second surface of each chip is bonded to the first surface of the carrier. A package has a first surface which is connected to the first sets of solder balls of the first and second chips. A high signal density bridge element having high signal density wiring on one or more layers is connected to the second sets of solder balls of the first and second chips. The bridge element is disposed between the first surface of the package and the first surfaces of the first and second chips.


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