The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 09, 2021
Filed:
Dec. 05, 2019
Semiconductor device packages and stacked package assemblies including high density interconnections
Advanced Semiconductor Engineering, Inc., Kaohsiung, TW;
John Richard Hunt, Kaohsiung, TW;
William T. Chen, Kaohsiung, TW;
Chih-Pin Hung, Kaohsiung, TW;
Chen-Chao Wang, Kaohsiung, TW;
ADVANCED SEMICONDUCTOR ENGINEERING, INC., Kaohsiung, TW;
Abstract
A semiconductor device package includes: a redistribution stack including a dielectric layer defining a first opening; and a redistribution layer (RDL) disposed over the dielectric layer and including a first trace, wherein the first trace includes a first portion extending over the dielectric layer along a first longitudinal direction adjacent to the first opening, and a second portion disposed in the first opening and extending from the first portion of the first trace, wherein the second portion of the first trace has a maximum width along a first transverse direction orthogonal to the first longitudinal direction, the first opening in the dielectric layer has a maximum width along the first transverse direction, and the maximum width of the second portion of the first trace is less than the maximum width of the first opening.