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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10903315 B1

PDFFull Text
Date of Patent:
Jan. 26, 2021

Filed:

Sep. 28, 2018

Formation of dielectric layer as etch-stop for source and drain epitaxy disconnection

Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Nicolas Loubet, Guilderland, NY (US);

Robin Hsin Kuo Chao, Cohoes, NY (US);

Julien Frougier, Albany, NY (US);

Ruilong Xie, Schenectady, NY (US);

Assignee:

INTERNATIONAL BUSINESS MACHINES CORPORATION, Armonk, NY (US);

Attorneys:

Cantor Colburn LLP

Joseph Petrokaitis

Primary Examiner:

Raj R Gupta

Int. Cl.
CPC ...
H01L 29/06 (2006.01); H01L 29/51 (2006.01); H01L 29/66 (2006.01); H01L 21/768 (2006.01); H01L 21/308 (2006.01); H01L 29/08 (2006.01); H01L 29/78 (2006.01);
U.S. Cl.
CPC ...
H01L 29/0649 (2013.01); H01L 21/3086 (2013.01); H01L 21/76829 (2013.01); H01L 29/0673 (2013.01); H01L 29/0847 (2013.01); H01L 29/517 (2013.01); H01L 29/6681 (2013.01); H01L 29/66545 (2013.01); H01L 29/7851 (2013.01);
Abstract

A technique relates to a semiconductor device. A bottom sacrificial layer is formed on a substrate. A stack is formed over the bottom sacrificial layer and a dummy gate is formed over the stack. The bottom sacrificial layer is removed from under the stack so as to leave an opening. An isolation layer is formed in the opening, the isolation layer being positioned between the stack and the substrate.

Find Patent Forward Citations

Loubet, Nicolas. (2021). Formation of dielectric layer as etch-stop for source and drain epitaxy disconnection (U.S. Patent No. 10903315). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/10903315

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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