The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 26, 2021

Filed:

Nov. 05, 2019
Applicant:

Mediatek Inc., Hsinchu, TW;

Inventors:

Chia-Cheng Chang, Hsin-Chu, TW;

I-Hsuan Peng, Hsin-Chu, TW;

Tzu-Hung Lin, Hsin-Chu, TW;

Assignee:

MEDIATEK INC, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 25/18 (2006.01); H01L 21/78 (2006.01); H01L 25/00 (2006.01); H01L 23/00 (2006.01); H01L 25/065 (2006.01); H01L 23/538 (2006.01);
U.S. Cl.
CPC ...
H01L 25/18 (2013.01); H01L 21/78 (2013.01); H01L 24/32 (2013.01); H01L 24/48 (2013.01); H01L 24/49 (2013.01); H01L 25/0655 (2013.01); H01L 25/50 (2013.01); H01L 23/5384 (2013.01); H01L 24/13 (2013.01); H01L 24/16 (2013.01); H01L 24/29 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/16235 (2013.01); H01L 2224/32106 (2013.01); H01L 2224/32137 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/48011 (2013.01); H01L 2224/48227 (2013.01); H01L 2224/49175 (2013.01); H01L 2224/49176 (2013.01); H01L 2924/1431 (2013.01); H01L 2924/1432 (2013.01); H01L 2924/1436 (2013.01); H01L 2924/15311 (2013.01);
Abstract

A semiconductor package assembly and method for forming the same are provided. The semiconductor package assembly includes a first semiconductor die and a second semiconductor die disposed on a first surface of a substrate. The first semiconductor die includes a peripheral region having a second edge facing the first edge of the second semiconductor die and a third edge opposite to the second edge, a circuit region surrounded by the peripheral region, wherein the circuit region has a fourth edge adjacent to the second edge and a fifth edge adjacent to the third edge. A minimum distance between the second edge and the fourth edge is a first distance, a minimum distance between the third edge and the fifth edge is a second distance, and the first distance is different from the second distance.


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