The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 12, 2021

Filed:

Dec. 11, 2019
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;

Inventors:

Chang-Chen Tsao, Tainan, TW;

Kuo Liang Lu, Hsinchu, TW;

Ru-Liang Lee, Hsinchu, TW;

Sheng-Hsiang Chuang, Hsin-Chu, TW;

Yu-Hung Cheng, Tainan, TW;

Yeur-Luen Tu, Taichung, TW;

Cheng-Kang Hu, Kaohsiung, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
B32B 38/10 (2006.01); H01L 21/67 (2006.01); H01L 21/68 (2006.01); H01L 21/683 (2006.01);
U.S. Cl.
CPC ...
B32B 38/10 (2013.01); H01L 21/67011 (2013.01); H01L 21/67092 (2013.01); H01L 21/681 (2013.01); H01L 21/6835 (2013.01); H01L 21/6838 (2013.01);
Abstract

The present disclosure relates to a debonding apparatus. In some embodiments, the debonding apparatus comprises a wafer chuck configured to hold a pair of bonded substrates on a chuck top surface. The debonding apparatus further comprises a pair of separating blades including a first separating blade and a second separating blade placed at edges of the pair of bonded substrates. The first separating blade has a first thickness that is smaller than a second thickness of the second separating blade. The debonding apparatus further comprises a flex wafer assembly configured to pull the pair of bonded substrates upwardly to separate a second substrate from a first substrate of the pair of bonded substrate. By providing unbalanced initial torques on opposite sides of the bonded substrate pair, edge defects and wafer breakage are reduced.


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