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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10886173 B1

PDFFull Text
Date of Patent:
Jan. 05, 2021

Filed:

Mar. 19, 2019

Platform and method of operating for integrated end-to-end fully self-aligned interconnect process

Applicant:

Tokyo Electron Limited, Tokyo, JP;

Inventors:

Robert Clark, Albany, NY (US);

Kandabara Tapily, Albany, NY (US);

Kai-Hung Yu, Albany, NY (US);

Assignee:

Tokyo Electron Limited, Tokyo, JP;

Attorney:

Oblon, McClelland, Maier & Neustadt, L.L.P.

Primary Examiner:

Bradley Smith

Int. Cl.
CPC ...
H01L 21/76 (2006.01); H01L 21/768 (2006.01); H01L 21/67 (2006.01); H01L 21/66 (2006.01); H01L 21/677 (2006.01); H01L 21/02 (2006.01); H01L 21/285 (2006.01); H01L 21/311 (2006.01); G05B 13/02 (2006.01); G05B 19/418 (2006.01); C23C 14/24 (2006.01); C23C 14/34 (2006.01); H01J 37/32 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76879 (2013.01); G05B 13/027 (2013.01); G05B 19/41875 (2013.01); H01L 21/0228 (2013.01); H01L 21/02271 (2013.01); H01L 21/28562 (2013.01); H01L 21/31116 (2013.01); H01L 21/67023 (2013.01); H01L 21/67063 (2013.01); H01L 21/67161 (2013.01); H01L 21/67167 (2013.01); H01L 21/67184 (2013.01); H01L 21/67196 (2013.01); H01L 21/67225 (2013.01); H01L 21/67253 (2013.01); H01L 21/67276 (2013.01); H01L 21/67288 (2013.01); H01L 21/67703 (2013.01); H01L 21/67742 (2013.01); H01L 21/67745 (2013.01); H01L 21/7685 (2013.01); H01L 21/76802 (2013.01); H01L 21/76831 (2013.01); H01L 21/76832 (2013.01); H01L 21/76834 (2013.01); H01L 21/76897 (2013.01); H01L 22/12 (2013.01); C23C 14/24 (2013.01); C23C 14/34 (2013.01); G05B 2219/32368 (2013.01); G05B 2219/45031 (2013.01); H01J 37/32 (2013.01); H01L 21/67017 (2013.01); H01L 21/67207 (2013.01);
Abstract

A method for forming a fully self-aligned via is provided. A workpiece having a pattern of features in a dielectric layer is received into a common manufacturing platform. Metal caps are deposited on the metal features, and a barrier layer is deposited on the metal caps. A first dielectric layer is added to exposed dielectric material. The barrier layer is removed and an etch stop layer is added on the exposed surfaces of the first dielectric layer and the metal caps. Additional dielectric material is added on top of the etch stop layer, then both the additional dielectric material and a portion of the etch stop layer are etched to form a feature to be filled with metal material. An integrated sequence of processing steps is executed within one or more common manufacturing platforms to provide controlled environments. Transfer modules transfer the workpiece between processing modules within and between controlled environments.

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