The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 29, 2020
Filed:
Mar. 08, 2019
Method for making a semiconductor device including enhanced contact structures having a superlattice
Atomera Incorporated, Los Gatos, CA (US);
Robert John Stephenson, Duxford, GB;
Richard Burton, Phoenix, AZ (US);
Dmitri Choutov, Sunnyvale, CA (US);
Nyles Wynn Cody, Tempe, AZ (US);
Daniel Connelly, San Francisco, CA (US);
Robert J. Mears, Wellesley, MA (US);
Erwin Trautmann, San Jose, CA (US);
ATOMERA INCORPORATED, Los Gatos, CA (US);
Abstract
A method for making a semiconductor device may include forming a trench in a semiconductor substrate, and forming a superlattice liner covering bottom and sidewall portions of the trench. The superlattice liner may include a plurality of stacked groups of layers, with each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The method may further include forming a semiconductor cap layer on the superlattice liner and having a dopant constrained therein by the superlattice liner, and forming a conductive body within the trench.