The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 29, 2020

Filed:

Aug. 29, 2017
Applicant:

Taiwan Semiconductor Manufacturing Company Ltd., Hsinchu, TW;

Inventors:

Hung-Ling Shih, Tainan, TW;

Yong-Shiuan Tsair, Tainan, TW;

Po-Wei Liu, Tainan, TW;

Wen-Tuo Huang, Tainan, TW;

Yu-Ling Hsu, Tainan, TW;

Chieh-Fei Chiu, Tainan, TW;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/11517 (2017.01); H01L 29/78 (2006.01); H01L 29/06 (2006.01); H01L 21/8234 (2006.01); H01L 29/51 (2006.01); H01L 29/423 (2006.01); H01L 27/11521 (2017.01);
U.S. Cl.
CPC ...
H01L 27/11517 (2013.01); H01L 21/823481 (2013.01); H01L 27/11521 (2013.01); H01L 29/0649 (2013.01); H01L 29/42328 (2013.01); H01L 29/513 (2013.01); H01L 29/7831 (2013.01);
Abstract

A method for forming a semiconductor structure includes providing a substrate including a plurality of first isolation structures formed therein, wherein the first isolation structures are protruded from a surface of the substrate; conformally forming a semiconductor layer over the substrate and the first isolation structures; forming a sacrificial layer over the semiconductor layer to form a planar surface over the substrate; and removing the sacrificial layer, a portion of the semiconductor layer and a portion of each first isolation structure to form at least one first gate structure using a same etchant.


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