The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 29, 2020
Filed:
Apr. 10, 2019
Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;
Kuo-Cheng Ching, Hsinchu County, TW;
Kuan-Lun Cheng, Hsin-Chu, TW;
Chih-Hao Wang, Hsinchu County, TW;
Sai-Hooi Yeong, Hsinchu County, TW;
Tzer-Min Shen, Hsinchu, TW;
Chi-Hsing Hsu, New Taipei, TW;
Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;
Abstract
Devices and methods of forming a FET including a substrate having a first fin and a second fin extending therefrom. A high-k gate dielectric layer and a ferroelectric insulator layer are deposited over the first fin and the second fin. In some embodiments, a dummy gate layer is deposited over the ferroelectric insulator layer over the first fin and the second fin to form a first gate stack over the first fin and a second gate stack over the second fin. The dummy gate layer of the first gate stack is then removed (while maintaining the ferroelectric insulator layer) to form a first trench. And the dummy gate layer and the ferroelectric insulator layer of the second gate stack are removed to form a second trench. At least one metal gate layer is formed in the first trench and the second trench.