The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 29, 2020

Filed:

May. 05, 2015
Applicant:

Advanced Semiconductor Engineering, Inc., Kaohsiung, TW;

Inventors:

Tien-Szu Chen, Kaohsiung, TW;

Sheng-Ming Wang, Kaohsiung, TW;

Kuang-Hsiung Chen, Kaohsiung, TW;

Yu-Ying Lee, Kaohsiung, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/498 (2006.01); H01L 23/495 (2006.01); H01L 21/48 (2006.01);
U.S. Cl.
CPC ...
H01L 23/49816 (2013.01); H01L 21/4828 (2013.01); H01L 23/49503 (2013.01); H01L 23/49534 (2013.01); H01L 23/49582 (2013.01); H01L 23/49811 (2013.01); H01L 23/49833 (2013.01); H01L 23/49861 (2013.01); H01L 23/49894 (2013.01); H01L 2224/16225 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/48091 (2013.01); H01L 2224/48227 (2013.01); H01L 2224/73265 (2013.01); H01L 2924/15311 (2013.01); H01L 2924/181 (2013.01);
Abstract

A substrate, a semiconductor package thereof and a process of making the same are provided. The substrate comprises an upper circuit layer and a lower circuit layer, the upper circuit layer comprising at least one trace and at least one pad and the lower circuit layer comprising at least one trace and at least one pad, wherein the trace of the upper circuit layer and the trace of the lower circuit layer are not aligned.


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