The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 29, 2020

Filed:

Jul. 17, 2019
Applicant:

Disco Corporation, Tokyo, JP;

Inventors:

Shigenori Harada, Tokyo, JP;

Takashi Okamura, Tokyo, JP;

Jinyan Zhao, Tokyo, JP;

Assignee:

DISCO CORPORATION, Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/78 (2006.01); H01L 21/683 (2006.01); C08J 5/18 (2006.01); H01L 21/67 (2006.01);
U.S. Cl.
CPC ...
H01L 21/78 (2013.01); C08J 5/18 (2013.01); H01L 21/67092 (2013.01); H01L 21/67103 (2013.01); H01L 21/67132 (2013.01); H01L 21/6835 (2013.01); H01L 21/6836 (2013.01); H01L 21/6838 (2013.01); C08J 2323/06 (2013.01); C08J 2323/12 (2013.01); C08J 2325/06 (2013.01); C08J 2367/02 (2013.01); H01L 21/67109 (2013.01); H01L 2221/68327 (2013.01); H01L 2221/68381 (2013.01); H01L 2221/68386 (2013.01);
Abstract

A wafer processing method includes: a wafer providing step of providing a wafer by placing a thermoplastic polymer sheet on an upper surface of a substrate on which the wafer is supported and positioning a back surface of the wafer on an upper surface of the polymer sheet; a sheet thermocompression bonding step of evacuating an enclosing environment in which the wafer is provided through the polymer sheet on the substrate, heating the polymer sheet, and pressing the wafer toward the polymer sheet to pressure-bond the wafer through the polymer sheet to the substrate; and a dividing step of positioning a cutting blade on the front surface of the wafer and cutting the wafer along the division lines to divide the wafer into individual device chips.


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