Operation assist circuit, memory device and operation assist method

Abstract

An operation assist circuit includes a precharge and equalization circuit, a first sharing switch and a second sharing switch. The precharge and equalization circuit is coupled between a first dummy bit line and a second dummy bit line of a dummy bit line pair and configured to precharge and equalize the first dummy bit line and the second dummy bit line. The first sharing switch is coupled between a first bit line of a bit line pair and the first dummy bit line of the dummy bit line pair. The first sharing switch is configured to control an electrical connection between the first bit line of the first bit line pair and the first dummy bit line of the dummy bit line pair according to a charge sharing control signal. The second sharing switch, coupled between a second bit line of the bit line pair and the second dummy bit line of the dummy bit line pair. The second sharing switch is configured to control an electrical connection between the second bit line of the bit line pair and the second dummy bit line of the dummy bit line pair according the charge sharing control signal.