The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 22, 2020

Filed:

Oct. 07, 2019
Applicant:

Taiwan Semiconductor Manufacturing Company Limited, Hsin-Chu, TW;

Inventors:

Krishna Kumar Bhuwalka, Hsin-Chu, TW;

Gerben Doornbos, Hsin-Chu, TW;

Matthias Passlack, Hsin-Chu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 29/739 (2006.01); H01L 29/775 (2006.01); H01L 29/06 (2006.01); B82Y 10/00 (2011.01); H01L 29/423 (2006.01); H01L 29/78 (2006.01); H01L 29/10 (2006.01); H01L 29/205 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66977 (2013.01); B82Y 10/00 (2013.01); H01L 29/068 (2013.01); H01L 29/0657 (2013.01); H01L 29/0676 (2013.01); H01L 29/0688 (2013.01); H01L 29/1037 (2013.01); H01L 29/1054 (2013.01); H01L 29/205 (2013.01); H01L 29/42372 (2013.01); H01L 29/66356 (2013.01); H01L 29/66439 (2013.01); H01L 29/66522 (2013.01); H01L 29/66666 (2013.01); H01L 29/7391 (2013.01); H01L 29/775 (2013.01); H01L 29/7827 (2013.01);
Abstract

Among other things, one or more techniques for forming a vertical tunnel field effect transistor (FET), and a resulting vertical tunnel FET are provided herein. In an embodiment, the vertical tunnel FET is formed by forming a core over a first type substrate region, forming a second type channel shell around a circumference greater than a core circumference, forming a gate dielectric around a circumference greater than the core circumference, forming a gate electrode around a circumference greater than the core circumference, and forming a second type region over a portion of the second type channel shell, where the second type has a doping opposite a doping of the first type. In this manner, line tunneling is enabled, thus providing enhanced tunneling efficiency for a vertical tunnel FET.


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