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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10872815 B1

PDFFull Text
Date of Patent:
Dec. 22, 2020

Filed:

Apr. 27, 2020

Conductive interconnect structures in integrated circuits

Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Jung-Tang Wu, Kaohsiung, TW;

Shao Tzu Lien, Tainan, TW;

Chi-Hung Liao, Hsinchu, TW;

Szu-Hua Wu, Zhubei, TW;

Liang-Yueh Ou Yang, New Taipei, TW;

Chin-Szu Lee, Taoyuan, TW;

Assignee:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Attorney:

Slater Matsil, LLP

Primary Examiner:

Brook Kebede

Int. Cl.
CPC ...
H01L 21/4763 (2006.01); H01L 21/768 (2006.01); H01J 37/32 (2006.01); H01L 21/67 (2006.01); H01L 23/522 (2006.01); H01L 29/66 (2006.01); H01L 21/8234 (2006.01); H01L 27/088 (2006.01); H01L 29/78 (2006.01); H01L 23/532 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76873 (2013.01); H01J 37/32357 (2013.01); H01L 21/67057 (2013.01); H01L 21/76843 (2013.01); H01L 21/823431 (2013.01); H01L 23/5226 (2013.01); H01L 23/53209 (2013.01); H01L 27/0886 (2013.01); H01L 29/66545 (2013.01); H01L 29/66795 (2013.01); H01L 29/785 (2013.01);
Abstract

An interconnect structure and a method of forming the interconnect structure are provided. A dielectric layer and openings therein are formed over a substrate. A conductive seed layer is formed over the top surface and along a bottom and sidewalls of the openings. A conductive fill layer is formed over the seed layer. Metal oxide on the surface of the seed layer may be reduced/removed by a surface pre-treatment. The cleaned surface is covered by depositing fill material over the seed layer without exposing the surface to oxygen. The surface treatment may include a reactive remote plasma clean using hydrogen radicals. If electroplating is used to deposit the fill layer, then the surface treatment may include soaking the substrate in the electrolyte before turning on the electroplating current. Other surface treatments may include active pre-clean (APC) using hydrogen radicals; or Ar sputtering using a metal clean version xT (MCxT) tool.

Find Patent Forward Citations

Wu, Jung-Tang. (2020). Conductive interconnect structures in integrated circuits (U.S. Patent No. 10872815). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/10872815

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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