The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 15, 2020

Filed:

Dec. 03, 2019
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Chun Chieh Wang, Kaohsiung, TW;

Zheng-Yang Pan, Zhubei, TW;

Shih-Chieh Chang, Taipei, TW;

Cheng-Han Lee, New Taipei, TW;

Huai-Tei Yang, Hsinchu, TW;

Shahaji B. More, Hsinchu, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/28 (2006.01); H01L 29/66 (2006.01); H01L 27/092 (2006.01); H01L 21/3215 (2006.01); H01L 29/51 (2006.01); H01L 29/78 (2006.01); H01L 29/49 (2006.01); H01L 21/8238 (2006.01);
U.S. Cl.
CPC ...
H01L 21/28185 (2013.01); H01L 21/28088 (2013.01); H01L 21/28247 (2013.01); H01L 21/3215 (2013.01); H01L 21/823821 (2013.01); H01L 21/823857 (2013.01); H01L 27/0924 (2013.01); H01L 29/4966 (2013.01); H01L 29/517 (2013.01); H01L 29/66795 (2013.01); H01L 29/785 (2013.01); H01L 21/28194 (2013.01);
Abstract

A FinFET device and method of forming the same are disclosed. The method includes forming a gate dielectric layer and depositing a metal oxide layer over the gate dielectric layer. The method also includes annealing the gate dielectric layer and the metal oxide layer, causing ions to diffuse from the metal oxide layer to the gate dielectric layer to form a doped gate dielectric layer. The method also includes forming a work function layer over the doped gate dielectric layer, and forming a gate electrode over the work function layer.


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