The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 15, 2020

Filed:

Feb. 24, 2020
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;

Inventors:

Chun-Yen Lin, Hsinchu, TW;

Bao-Ru Young, Zhubei, TW;

Tung-Heng Hsieh, Zhudong Township, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 30/392 (2020.01); H01L 29/78 (2006.01); H01L 27/088 (2006.01);
U.S. Cl.
CPC ...
G06F 30/392 (2020.01); H01L 27/0886 (2013.01); H01L 29/7831 (2013.01);
Abstract

In some embodiments, the present disclosure relates to a method that includes receiving an initial layout design for a circuit schematic. The initial layout design includes a first gate electrode, a second gate electrode, and a third gate electrode arranged over a continuous fin. A first source/drain region is arranged between the first gate electrode and dummy gate electrode, and a second source/drain region is arranged between the second gate electrode and the dummy gate electrode. The method further includes determining if at least one of the first or second source/drain regions corresponds to a drain in the circuit schematic, and modifying the initial layout design to increase a dummy threshold voltage associated with the dummy gate electrode when the at least one of the first or second source/drain regions corresponds to the drain in the circuit schematic to provide a modified layout design.


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