The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 08, 2020

Filed:

May. 06, 2019
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Kuan-Lun Cheng, Hsin-Chu, TW;

Li-Shyue Lai, Hsinchu County, TW;

Ching-Wei Tsai, Hsinchu, TW;

Kai-Chieh Yang, Kaohsiung, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 21/28 (2006.01); H01L 29/40 (2006.01); H01L 29/51 (2006.01); H01L 29/423 (2006.01); H01L 21/311 (2006.01); H01L 29/49 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66795 (2013.01); H01L 21/28158 (2013.01); H01L 21/31144 (2013.01); H01L 29/401 (2013.01); H01L 29/42364 (2013.01); H01L 29/42368 (2013.01); H01L 29/513 (2013.01); H01L 29/517 (2013.01); H01L 29/66545 (2013.01); H01L 29/4966 (2013.01); H01L 29/518 (2013.01);
Abstract

Examples of an integrated circuit with a gate stack and a method for forming the integrated circuit are provided herein. In some examples, a method includes receiving a workpiece that includes: a pair of sidewall spacers disposed over a channel region, a gate dielectric disposed on the channel region and extending along a vertical surface of a first spacer of the pair of sidewall spacers, and a capping layer disposed on the high-k gate dielectric and extending along the vertical surface. A shaping feature is formed on the capping layer and the high-k gate dielectric. A first portion of the high-k gate dielectric and a first portion of the capping layer disposed between the shaping feature and the first spacer are removed to leave a second portion of the high-k gate dielectric and a second portion of the capping layer extending along the vertical surface.


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