The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 08, 2020

Filed:

Dec. 10, 2018
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Kuo Lung Pan, Hsinchu, TW;

Wei Sen Chang, Jinsha Township, TW;

Tin-Hao Kuo, Hsinchu, TW;

Hao-Yi Tsai, Hsinchu, TW;

Chung-Shi Liu, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 25/065 (2006.01); H01L 23/00 (2006.01); H01L 23/495 (2006.01); H01L 23/498 (2006.01); H01L 23/31 (2006.01); H01L 21/48 (2006.01); H01L 21/56 (2006.01); H01L 23/538 (2006.01); H01L 25/00 (2006.01);
U.S. Cl.
CPC ...
H01L 25/0652 (2013.01); H01L 21/4825 (2013.01); H01L 21/56 (2013.01); H01L 23/3114 (2013.01); H01L 23/3121 (2013.01); H01L 23/49506 (2013.01); H01L 23/49579 (2013.01); H01L 23/49827 (2013.01); H01L 23/5389 (2013.01); H01L 24/02 (2013.01); H01L 24/08 (2013.01); H01L 24/19 (2013.01); H01L 24/24 (2013.01); H01L 24/82 (2013.01); H01L 25/065 (2013.01); H01L 25/50 (2013.01); H01L 2224/0231 (2013.01); H01L 2224/0239 (2013.01); H01L 2224/02372 (2013.01); H01L 2224/02373 (2013.01); H01L 2224/02379 (2013.01); H01L 2224/04105 (2013.01); H01L 2224/12105 (2013.01); H01L 2224/215 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/73267 (2013.01); H01L 2224/821 (2013.01); H01L 2225/06548 (2013.01); H01L 2225/06582 (2013.01); H01L 2924/01029 (2013.01); H01L 2924/18161 (2013.01); H01L 2924/18162 (2013.01);
Abstract

A method for forming through vias comprises the steps of forming a dielectric layer over a package and forming an RDL over the dielectric layer, wherein forming the RDL includes the steps of forming a seed layer, forming a first patterned mask over the seed layer, and performing a first metal plating. The method further includes forming through vias on top of a first portion of the RDL, wherein forming the through vias includes forming a second patterned mask over the seed layer and the RDL, and performing a second metal plating. The method further includes attaching a chip to a second portion of the RDL, and encapsulating the chip and the through vias in an encapsulating material.


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