The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 08, 2020
Filed:
May. 01, 2019
Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;
Shih Kuang Yang, Tainan, TW;
Ping-Cheng Li, Kaohsiung, TW;
Hung-Ling Shih, Tainan, TW;
Po-Wei Liu, Tainan, TW;
Wen-Tuo Huang, Tainan, TW;
Yu-Ling Hsu, Tainan, TW;
Yong-Shiuan Tsair, Tainan, TW;
Chia-Sheng Lin, Tainan, TW;
Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;
Abstract
Various embodiments of the present application are directed towards an integrated memory chip with an enhanced device-region layout for reduced leakage current and an enlarged word-line etch process window (e.g., enhanced word-line etch resiliency). In some embodiments, the integrated memory chip comprises a substrate, a control gate, a word line, and an isolation structure. The substrate comprises a first source/drain region. The control gate and the word line are on the substrate. The word line is between and borders the first source/drain region and the control gate and is elongated along a length of the word line. The isolation structure extends into the substrate and has a first isolation-structure sidewall. The first isolation-structure sidewall extends laterally along the length of the word line and underlies the word line.