The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 01, 2020

Filed:

Oct. 23, 2019
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Subramaniam Maiyuran, Gold River, CA (US);

Sanjeev S. Jahagirdar, Folsom, CA (US);

Kiran C. Veernapu, Bangalore, IN;

Eric J. Asperheim, El Dorado Hills, CA (US);

Altug Koker, El Dorado Hills, CA (US);

Balaji Vembu, Folsom, CA (US);

Joydeep Ray, Folsom, CA (US);

Abhishek R. Appu, El Dorado Hills, CA (US);

Assignee:

Intel Corporation, Santa Clara, unknown;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 15/00 (2006.01); G06F 1/3234 (2019.01); G06F 9/46 (2006.01); G06F 1/329 (2019.01);
U.S. Cl.
CPC ...
G06F 1/3243 (2013.01); G06F 1/329 (2013.01); G06F 9/46 (2013.01);
Abstract

Methods and apparatus relating to techniques for a dual path sequential element to reduce toggles in data path are described. In an embodiment, switching logic causes signals for a single data path of a processor to be directed to at least two separate data paths. At least one of the two separate data paths is power gated to reduce signal toggles in the at least one data path. Other embodiments are also disclosed and claimed.


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