The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 17, 2020

Filed:

Aug. 28, 2018
Applicant:

Indian Institute of Science, Bangalore, IN;

Inventors:

Mayank Shrivastava, Bangalore, IN;

Sayak Dutta Gupta, Bangalore, IN;

Ankit Soni, Bangalore, IN;

Srinivasan Raghavan, Bangalore, IN;

Navakanta Bhat, Bangalore, IN;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/49 (2006.01); H01L 29/778 (2006.01); H01L 21/02 (2006.01); H01L 29/51 (2006.01); H01L 29/66 (2006.01); H01L 29/423 (2006.01); H01L 29/10 (2006.01); H01L 29/20 (2006.01);
U.S. Cl.
CPC ...
H01L 29/4983 (2013.01); H01L 21/0228 (2013.01); H01L 21/02178 (2013.01); H01L 21/02186 (2013.01); H01L 21/02194 (2013.01); H01L 29/517 (2013.01); H01L 29/66462 (2013.01); H01L 29/7786 (2013.01); H01L 29/1066 (2013.01); H01L 29/2003 (2013.01); H01L 29/4236 (2013.01);
Abstract

The present disclosure provides an improved enhancement mode field effect transistor (FET) having an oxide (AlTiO) emulating p-type gate. The present disclosure provides a novel enhancement mode High Electron Mobility Transistor (HEMT) structure with AlTiO Gate Oxide Engineering as Replacement of p-GaN Gate. In an aspect, the present disclosure provides a hybrid gate stack that combines p-GaN technology with the proposed oxide for e-mode operation. The HEMT structure with AlTiO Gate oxide provides a threshold voltage tuning from negative to positive by changing p-doping composition. Using a developed p-type oxide, e-mode device shows ON current ˜400 mA/mm, sub-threshold slope of 73 mV/dec, R=8.9 Ωmm, interface trap density <10mmeVand gate leakage below 200 nA/mm at the OFF-state breakdown.


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