The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 17, 2020

Filed:

Nov. 16, 2018
Applicant:

Atomera Incorporated, Los Gatos, CA (US);

Inventors:

Hideki Takeuchi, San Jose, CA (US);

Daniel Connelly, San Francisco, CA (US);

Marek Hytha, Brookline, MA (US);

Richard Burton, Phoenix, AZ (US);

Robert J. Mears, Wellesley, MA (US);

Assignee:

ATOMERA INCORPORATED, Los Gatos, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/225 (2006.01); H01L 21/283 (2006.01); H01L 21/265 (2006.01); H01L 29/15 (2006.01); H01L 29/08 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 29/45 (2006.01);
U.S. Cl.
CPC ...
H01L 29/152 (2013.01); H01L 21/2253 (2013.01); H01L 21/283 (2013.01); H01L 29/0847 (2013.01); H01L 29/66795 (2013.01); H01L 29/785 (2013.01); H01L 21/26533 (2013.01); H01L 29/45 (2013.01);
Abstract

A method for making a FINFET may include forming spaced apart source and drain regions in a semiconductor fin with a channel region extending therebetween. At least one of the source and drain regions may be divided into a lower region and an upper region by a dopant diffusion blocking superlattice with the upper region having a same conductivity and higher dopant concentration than the lower region. The method may further include forming a gate on the channel region, depositing at least one metal layer on the upper region, and applying heat to move upward non-semiconductor atoms from the non-semiconductor monolayers to react with the at least one metal layer to form a contact insulating interface between the upper region and adjacent portions of the at least one metal layer.


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