The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 17, 2020

Filed:

Aug. 21, 2019
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Charles L. Arvin, Poughkeepsie, NY (US);

Brian M. Erwin, Millbrook, NY (US);

Mark W. Kapfhammer, Poughkeepsie, NY (US);

Brian W. Quinlan, Poughkeepsie, NY (US);

Charles L. Reynolds, Red Hook, NY (US);

Thomas Weiss, Poughkeepsie, NY (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/52 (2006.01); H01L 21/56 (2006.01); H01L 25/065 (2006.01); H01L 23/522 (2006.01); H01L 23/13 (2006.01); H01L 25/00 (2006.01); H01L 23/538 (2006.01);
U.S. Cl.
CPC ...
H01L 25/065 (2013.01); H01L 23/13 (2013.01); H01L 23/5384 (2013.01); H01L 23/5385 (2013.01); H01L 25/50 (2013.01);
Abstract

An integrated circuit (IC) chip carrier includes one or more memory devices therein. The memory is integrated into the carrier prior to the IC chip being connected to the carrier. Therefore, the IC chip may be connected to the memory at the same time as the IC chip is connected to the carrier. An access instruction may be sent from the IC chip to the memory through a wiring line of the IC chip carrier. Power potential may be sent from a system board to the memory through a vertical interconnect access (VIA). Alternatively, an access instruction may be sent from a first IC chip to the memory and power potential may be sent from a second IC chip to the memory.


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