The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 20, 2020
Filed:
Jul. 02, 2018
Amkor Technology, Inc., Tempe, AZ (US);
Dong Joo Park, Seoul, KR;
Jin Seong Kim, Seoul, KR;
Ki Wook Lee, Seoul, KR;
Dae Byoung Kang, Kyunggi-do, KR;
Ho Choi, Seoul, KR;
Kwang Ho Kim, Kyunggi-do, KR;
Jae Dong Kim, Seoul, KR;
Yeon Soo Jung, Seoul, KR;
Sung Hwan Cho, Kyunggi-do, KR;
Amkor Technology Singapore Holding Pte Ltd., Singapore, SG;
Abstract
In accordance with the present description, there is provided multiple embodiments of a semiconductor device. In each embodiment, the semiconductor device comprises a substrate having a conductive pattern formed thereon. In addition to the substrate, each embodiment of the semiconductor device includes at least one semiconductor die which is electrically connected to the substrate, both the semiconductor die and the substrate being at least partially covered by a package body of the semiconductor device. In certain embodiments of the semiconductor device, through-mold vias are formed in the package body to provide electrical signal paths from an exterior surface thereof to the conductive pattern of the substrate. In other embodiments, through mold vias are also included in the package body to provide electrical signal paths between the semiconductor die and an exterior surface of the package body. Other embodiments of the semiconductor device comprise one or more interposers which are electrically connected to the through-mold vias, and may be covered by the package body and/or disposed in spaced relation thereto. In yet other embodiments of the semiconductor device, the interposer may not be electrically connected to the through mold vias, but may have one or more semiconductor dies of the semiconductor device electrically connected thereto.