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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10796962 B1

PDFFull Text
Date of Patent:
Oct. 06, 2020

Filed:

Jun. 28, 2019

Semiconductor wafer processing method

Applicant:

Disco Corporation, Tokyo, JP;

Inventors:

Masatoshi Wakahara, Tokyo, JP;

Frank Wei, Tokyo, JP;

Assignee:

DISCO CORPORATION, Tokyo, JP;

Attorney:

Greer Burns & Crain Ltd.

Primary Examiner:

Andres Munoz

Int. Cl.
CPC ...
H01L 21/78 (2006.01); H01L 21/3065 (2006.01); H01L 21/308 (2006.01); H01L 21/02 (2006.01); H01L 23/00 (2006.01); H01L 21/268 (2006.01); H01L 21/283 (2006.01); H01L 21/304 (2006.01); H01L 21/31 (2006.01);
U.S. Cl.
CPC ...
H01L 21/78 (2013.01); H01L 21/0206 (2013.01); H01L 21/268 (2013.01); H01L 21/308 (2013.01); H01L 21/3065 (2013.01); H01L 24/11 (2013.01); H01L 21/283 (2013.01); H01L 21/3043 (2013.01); H01L 21/31 (2013.01); H01L 24/13 (2013.01); H01L 2224/1145 (2013.01); H01L 2224/1146 (2013.01); H01L 2224/13111 (2013.01); H01L 2224/13139 (2013.01); H01L 2224/13144 (2013.01); H01L 2224/13147 (2013.01); H01L 2224/13155 (2013.01); H01L 2224/13164 (2013.01);
Abstract

A semiconductor wafer processing method includes a step of forming a laser processed groove on the front side of a semiconductor wafer along each division line, a step of forming a mask layer on a protective layer except in an area above a metal electrode formed in each device on the front side of the wafer, a first etching step of etching the protective layer by using the mask layer to expose each metal electrode, a second etching step of etching the inner surface of each laser processed groove by using the mask layer used in the first etching step, thereby expanding each laser processed groove, and a dividing step of dividing the wafer along each laser processed groove expanded in the second etching step.

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