The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 06, 2020
Filed:
Apr. 19, 2019
Cadence Design Systems, Inc., San Jose, CA (US);
Jonathan R. Fales, Finksburg, MD (US);
Frank E. Gennari, Campbell, CA (US);
Jeffrey E. Nelson, Saratoga Springs, NY (US);
Jeffrey Russell, Livingston, TX (US);
Ya-Chieh Lai, Mountain View, CA (US);
Jac Paul Condella, Campbell, CA (US);
Cadence Design Systems, Inc., San Jose, CA (US);
Abstract
Systems, methods, media, and other such embodiments described herein relate to critical area analysis (CAA) operations as part of electronic design automation (EDA). One embodiment involves accessing a circuit design having a first layer (which may be a composite layer), sampling the first layer, and performing an initial CAA using the sampled portions of the layer with a set of predetermined defect sizes. The initial CAA is used to automatically generate a model which can be used to accurately select input parameters (e.g., selected defect sizes) for a full analysis. A CAA characteristic is then calculated for the first layer using the input parameters. In various embodiments, different sampling percentages and criteria for selecting input parameters can be used to reduce the computing resources to compute a CAA characteristic, such as theta-bar, while limiting error to a threshold amount (e.g. less than one percent).