The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 06, 2020
Filed:
Oct. 31, 2018
United Microelectronics Corp., Hsin-Chu, TW;
Fujian Jinhua Integrated Circuit Co., Ltd., Quanzhou, Fujian Province, CN;
Wei-Lun Hsu, Kaohsiung, TW;
Gang-Yi Lin, Taitung County, TW;
Yu-Hsiang Hung, Tainan, TW;
Ying-Chih Lin, Tainan, TW;
Feng-Yi Chang, Tainan, TW;
Ming-Te Wei, Changhua County, TW;
Shih-Fang Tzou, Tainan, TW;
Fu-Che Lee, Taichung, TW;
Chia-Liang Liao, Yunlin County, TW;
UNITED MICROELECTRONICS CORP., Hsin-Chu, TW;
Fujian Jinhua Integrated Circuit Co., Ltd., Quanzhou, Fujian Province, CN;
Abstract
A method of forming a layout definition of a semiconductor device includes the following steps. Firstly, a plurality of first patterns is established to form a material layer over a substrate, with the first patterns being regularly arranged in a plurality of columns along a first direction to form an array arrangement. Next, a plurality of second patterns is established to surround the first patterns. Then, a third pattern is established to form a blocking layer on the material layer, with the third pattern being overlapped with a portion of the second patterns and with at least one of the second patterns being partially exposed from the third pattern. Finally, the first patterns are used to form a plurality of first openings in a stacked structure on the substrate to expose a portion of the substrate respectively.