The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 22, 2020

Filed:

Dec. 01, 2017
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Francois Arguin, Bromont, CA;

Luc Guerin, Granby, CA;

Maryse Cournoyer, Granby, CA;

Steve E. Whitehead, Quebec, CA;

Jean Audet, Granby, CA;

Richard D. Langlois, Granby, CA;

Christian Bergeron, Granby, CA;

Pascale Gagnon, Brigham, CA;

Nathalie Meunier, St-Paul-d'Abbotsford, CA;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/538 (2006.01); H01L 25/18 (2006.01); H01L 23/498 (2006.01); H01L 25/065 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 23/5381 (2013.01); H01L 23/49827 (2013.01); H01L 23/49833 (2013.01); H01L 23/49883 (2013.01); H01L 23/49894 (2013.01); H01L 23/5384 (2013.01); H01L 24/17 (2013.01); H01L 25/0652 (2013.01); H01L 25/0655 (2013.01); H01L 25/18 (2013.01); H01L 24/13 (2013.01); H01L 24/16 (2013.01); H01L 2224/13147 (2013.01); H01L 2224/16113 (2013.01); H01L 2224/16145 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/16235 (2013.01); H01L 2224/16238 (2013.01); H01L 2224/1703 (2013.01); H01L 2224/17181 (2013.01); H01L 2224/17517 (2013.01); H01L 2225/06513 (2013.01); H01L 2225/06517 (2013.01); H01L 2225/06548 (2013.01); H01L 2924/1431 (2013.01); H01L 2924/1434 (2013.01); H01L 2924/15192 (2013.01); H01L 2924/15311 (2013.01);
Abstract

A package and system for high-density chip-to-chip interconnection is provided. Embodiments of the present invention utilizes a plurality of circuit dies including a laminate substrate adjacent to the plurality of circuit dies. It also includes a conductive spacer disposed between the laminate substrate and one of the plurality of circuit dies, a silicon bridge and a conductive interposer disposed between the laminate substrate and the plurality of dies and adjacent to the conductive spacer. Furthermore the embodiment of this present invention can include a top layer of a printed circuit board (PCB) coupled with a bottom layer of the laminate substrate. The conductive spacer comprises, at least of, a laminate, organic or copper material.


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