The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 22, 2020
Filed:
Oct. 08, 2018
Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;
Hui-Ting Yang, Zhubei, TW;
Chih-Ming Lai, Hsinchu, TW;
Chun-Kuang Chen, Guanxi Township, TW;
Chih-Liang Chen, Hsinchu, TW;
Charles Chew-Yuen Young, Cupertino, CA (US);
Jiann-Tyng Tzeng, Hsin Chu, TW;
Kam-Tou Sio, Zhubei, TW;
Meng-Hung Shen, Zhudong Township, TW;
Ru-Gun Liu, Zhubei, TW;
Wei-Cheng Lin, Taichung, TW;
Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;
Abstract
The present disclosure relates to an integrated chip. In some embodiments, the integrated chip has a first plurality of source and drain regions disposed within a substrate along a first line extending in a first direction. A plurality of gate structures are arranged over the substrate at a substantially regular pitch, and a plurality of middle-of-the-line (MOL) structures are respectively interleaved between adjacent ones of the plurality of gate structures. The plurality of MOL structures include MOL active structures that are electrically coupled to an overlying conductive interconnect and MOL dummy structures that are not electrically coupled to any overlying conductive interconnect. The plurality of MOL structures are arranged over the first plurality of source and drain regions at an irregular pitch that is larger than the substantially regular pitch.