Vertical insulated gate turn-off thyristor with intermediate p+ layer in p-base formed using epitaxial layer

Abstract

An insulated gate turn-off thyristor has a layered structure including a p+ layer (e.g., a substrate), an n-epi layer, a p-well, vertical insulated gate regions formed in the p-well, and an n− layer over the p-well and between the gate regions, so that vertical npn and pnp transistors are formed. After forming the p-well, boron ions are implanted into the exposed surface of the p-well to form a p+ region. The n-epi layer is then grown over the p-well and the p+ region, and the boron in the p+ region is diffused upward into the n-epi layer and downward to form an intermediate p+ region. The p-well's highly doped intermediate region enables improvement in the npn transistor efficiency as well as enabling more independent control over the characteristics of the n-type layer (emitter) and the overall dopant concentration and thickness of the p-type base to optimize the thyristor's performance.