The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 15, 2020
Filed:
Dec. 07, 2018
Infineon Technologies Ag, Neubiberg, DE;
Chau Fatt Chiang, Melaka, MY;
April Coleen Tuazon Bernardez, Melaka, MY;
Junny Abdul Wahid, Melaka, MY;
Roslie Saini bin Bakar, Melaka, MY;
Kon Hoe Chin, Pusing, MY;
Hock Heng Chong, Melaka, MY;
Kok Yau Chua, Melaka, MY;
Hsieh Ting Kuek, Melaka, MY;
Chee Hong Lee, Melaka, MY;
Soon Lee Liew, Ipoh, MY;
Nurfarena Othman, Melaka, MY;
Pei Luan Pok, Melaka, MY;
Werner Reiss, Raubling, DE;
Stefan Schmalzl, Sauerlach, DE;
Infineon Technologies AG, Neubiberg, DE;
Abstract
Embodiments of chip-package and corresponding methods of manufacture are provided. In an embodiment of a chip-package, the chip-package includes: a carrier having a first side and a second side opposing the first side; a first chip coupled to the first side of the carrier; a second chip coupled to the second side of the carrier; an encapsulation with a first portion, which at least partially encloses the first chip on the first side of the carrier, and a second portion, which at least partially encloses the second chip on the second side of the carrier; a via extending through the first portion of the encapsulation, the carrier and the second portion of the encapsulation; and an electrically conductive material at least partly covering a sidewall of the via in the first portion or the second portion of the encapsulation, to electrically contact the carrier at either side.