The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 15, 2020

Filed:

Nov. 09, 2016
Applicant:

United Microelectronics Corp., Hsin-Chu, TW;

Inventors:

Chih-Kai Kang, Tainan, TW;

Sheng-Yuan Hsueh, Tainan, TW;

Yi-Chung Sheng, Tainan, TW;

Kuo-Yu Liao, Kaohsiung, TW;

Shu-Hung Yu, Kaohsiung, TW;

Hung-Hsu Lin, Tainan, TW;

Hsiang-Hung Peng, Hsinchu County, TW;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/544 (2006.01); H01L 27/092 (2006.01); H01L 27/02 (2006.01); G03F 9/00 (2006.01); H01L 21/8238 (2006.01);
U.S. Cl.
CPC ...
H01L 23/544 (2013.01); G03F 9/7076 (2013.01); G03F 9/7084 (2013.01); H01L 27/0207 (2013.01); H01L 27/092 (2013.01); H01L 21/823871 (2013.01); H01L 2223/5442 (2013.01); H01L 2223/5446 (2013.01); H01L 2223/54406 (2013.01); H01L 2223/54426 (2013.01); H01L 2223/54433 (2013.01);
Abstract

A semiconductor device includes a substrate including a plurality of chip areas and a scribe line defined thereon, and a mark pattern disposed in the scribe line. The mark pattern includes a plurality of unit cells immediately adjacent to each other, and each unit cell includes a first active region, a second active region isolated from the first active region, a plurality of first gate structures extending along a first direction and arranged along a second direction perpendicular to the first direction, and a plurality of first conductive structures. The first gate structures straddle the first active region and the second active region. The first conductive structures are disposed on the first active region, the second active region, and two opposite sides of the first gate structures.


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