The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 15, 2020

Filed:

Feb. 26, 2019
Applicant:

United Microelectronics Corp., Hsin-Chu, TW;

Inventors:

Kuan-Ying Lai, Chiayi, TW;

Chang-Mao Wang, Tainan, TW;

Hsin-Yu Hsieh, Tainan, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/311 (2006.01); H01L 21/768 (2006.01); H01L 21/02 (2006.01); H01L 21/306 (2006.01); H01L 21/31 (2006.01); H01L 21/3065 (2006.01); H01L 21/3105 (2006.01); H01L 21/04 (2006.01); H01L 21/308 (2006.01);
U.S. Cl.
CPC ...
H01L 21/311 (2013.01); H01L 21/02019 (2013.01); H01L 21/02296 (2013.01); H01L 21/042 (2013.01); H01L 21/306 (2013.01); H01L 21/308 (2013.01); H01L 21/3065 (2013.01); H01L 21/30655 (2013.01); H01L 21/31 (2013.01); H01L 21/3105 (2013.01); H01L 21/31051 (2013.01); H01L 21/31053 (2013.01); H01L 21/31055 (2013.01); H01L 21/31105 (2013.01); H01L 21/31111 (2013.01); H01L 21/31116 (2013.01); H01L 21/76802 (2013.01); H01L 21/76837 (2013.01);
Abstract

A material layer having recesses is formed on a substrate including a high pattern density area and a low pattern density area. A first dielectric layer and a second dielectric layer are sequentially formed to cover the material layer, wherein a top surface of the first dielectric layer in the high pattern density area is higher than a top surface of the first dielectric layer in the low pattern density area, thereby a thickness of the second dielectric layer in the low pattern density area being thicker than a thickness of the second dielectric layer in the high pattern density area. An etching back process is performed to remove the second dielectric layer and the first dielectric layer, wherein the etching rate of the etching back process to the second dielectric layer is lower than the etching rate of the etching back process to the first dielectric layer.


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