The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 08, 2020
Filed:
Sep. 30, 2016
Applicant:
Intel Corporation, Santa Clara, CA (US);
Inventors:
Zhicheng Ding, Shanghai, CN;
Bin Liu, Shanghai, CN;
Yong She, Songjiang, CN;
Aiping Tan, Shanghai, CN;
Li Deng, Shanghai, CN;
Assignee:
Intel Corporation, Santa Clara, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/00 (2006.01); H01L 25/00 (2006.01); H01L 25/065 (2006.01); H01L 25/18 (2006.01); H01L 21/66 (2006.01); H01L 23/31 (2006.01);
U.S. Cl.
CPC ...
H01L 25/0657 (2013.01); H01L 22/12 (2013.01); H01L 22/32 (2013.01); H01L 24/49 (2013.01); H01L 25/18 (2013.01); H01L 25/50 (2013.01); H01L 23/3107 (2013.01); H01L 2224/32145 (2013.01); H01L 2224/73253 (2013.01); H01L 2225/0651 (2013.01); H01L 2225/06517 (2013.01); H01L 2225/06537 (2013.01); H01L 2225/06562 (2013.01); H01L 2225/06575 (2013.01); H01L 2225/06586 (2013.01); H01L 2225/06596 (2013.01); H01L 2924/181 (2013.01);
Abstract
A system in package includes a stair-stacked memory module that is stacked vertically with respect to a processor die. A spacer is used adjacent to the processor die to create a bridge for the stair-stacked memory module. Each memory die in the stair-stacked memory module includes a vertical bond wire that emerges from a matrix for connection. The matrix encloses the stair-stacked memory module and at least a portion of the processor die.