The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 08, 2020

Filed:

Jun. 27, 2019
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Ling-Wei Li, Hsinchu, TW;

Jung-Hua Chang, Hsinchu, TW;

Cheng-Lin Huang, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/00 (2006.01); H01L 21/768 (2006.01); H01L 23/522 (2006.01); H01L 23/482 (2006.01);
U.S. Cl.
CPC ...
H01L 24/81 (2013.01); H01L 21/76816 (2013.01); H01L 21/76871 (2013.01); H01L 23/4824 (2013.01); H01L 23/5226 (2013.01); H01L 24/09 (2013.01); H01L 24/11 (2013.01); H01L 24/17 (2013.01); H01L 2224/02333 (2013.01); H01L 2224/03914 (2013.01); H01L 2224/04 (2013.01); H01L 2224/0401 (2013.01);
Abstract

A method for forming a chip package structure is provided. The method includes forming a conductive via structure in a first substrate. The method includes bonding a chip to a first surface of the first substrate. The method includes forming a barrier layer over a second surface of the first substrate. The method includes forming a first insulating layer over the barrier layer. The method includes forming a conductive pad over the first insulating layer and in the first opening, the second opening, and the third opening. The conductive pad continuously extends from the conductive via structure into the third opening. The method includes forming a conductive bump over the conductive pad in the third opening.


Find Patent Forward Citations

Loading…