The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 01, 2020
Filed:
Jun. 03, 2019
Micron Technology, Inc., Boise, ID (US);
Aliasgar S. Madraswala, Folsom, CA (US);
Kristopher H. Gaewsky, El Dorado Hills, CA (US);
Naveen Vittal Prabhu, Folsom, CA (US);
Purval S. Sule, Folsom, CA (US);
Trupti Bemalkhedkar, Folsom, CA (US);
Nehul N. Tailor, Phoenix, AZ (US);
Quan H. Ngo, Elk Grove, CA (US);
Dheeraj Srinivasan, San Jose, CA (US);
Micron Technology, Inc., Boise, ID (US);
Abstract
Various embodiments, disclosed herein, can include apparatus and methods to perform a one check failure byte (CFBYTE) scheme in programming of a memory device. In programming memory cells in which each memory cell can store multiple bits, the multiple bits being a n-tuple of bits of a set of n-tuples of bits with each n-tuple of the set associated with a level of a set of levels of threshold voltages for the memory cells. Verification of a program algorithm can be structured based on a programming algorithm that proceeds in a progressive manner by placing a threshold voltage of one level/distribution at a time. The routine of this progression can be used to perform just one failure byte check for that specific target distribution only, thus eliminating the need to check failure byte for all subsequent target distribution during every stage of program algorithm. Additional apparatus, systems, and methods are disclosed.