The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 18, 2020

Filed:

Oct. 04, 2018
Applicants:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

National Taiwan University, Taipei, TW;

Inventors:

Yu-Shiang Huang, New Taipei, TW;

Hung-Yu Yeh, Taichung, TW;

Wen Hung Huang, Tainan, TW;

Chee-Wee Liu, Taipei, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/12 (2006.01); H01L 27/088 (2006.01); H01L 29/423 (2006.01); H01L 21/8234 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 27/1207 (2013.01); H01L 21/823412 (2013.01); H01L 21/823418 (2013.01); H01L 21/823437 (2013.01); H01L 21/823481 (2013.01); H01L 27/088 (2013.01); H01L 29/42392 (2013.01); H01L 29/6656 (2013.01);
Abstract

A MOSFET structure including stacked vertically isolated MOSFETs and a method for forming the same are disclosed. In an embodiment, the method may include depositing a first buffer layer over a substrate; depositing a first channel layer over the first buffer layer; depositing a second buffer layer over the first channel layer; depositing a second channel layer over the second buffer layer; depositing a third buffer layer over the second channel layer; etching the first buffer layer, the first channel layer, the second buffer layer, the second channel layer, and the third buffer layer to form a fin structure; etching the first buffer layer, the second buffer layer, and the third buffer layer to form a first plurality of openings; forming a first gate stack in the first opening disposed in the first buffer layer, a second gate stack in the first opening disposed in the second buffer layer, and a third gate stack in the first opening disposed in the third buffer layer; and replacing the second buffer layer and a portion of the second gate stack with an isolation structure.


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