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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10741639 B1

PDFFull Text
Date of Patent:
Aug. 11, 2020

Filed:

Sep. 28, 2018

Formation of dielectric layer as etch-stop for source and drain epitaxy disconnection

Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Nicolas Loubet, Guilderland, NY (US);

Robin Hsin Kuo Chao, Cohoes, NY (US);

Julien Frougier, Albany, NY (US);

Ruilong Xie, Schenectady, NY (US);

Assignee:

INTERNATIONAL BUSINESS MACHINES CORPORATION, Armonk, NY (US);

Attorneys:

Cantor Colburn LLP

Joseph Petrokaitis

Primary Examiner:

Raj R Gupta

Int. Cl.
CPC ...
H01L 29/06 (2006.01); H01L 29/51 (2006.01); H01L 29/66 (2006.01); H01L 21/768 (2006.01); H01L 29/08 (2006.01); H01L 21/308 (2006.01); H01L 29/78 (2006.01);
U.S. Cl.
CPC ...
H01L 29/0649 (2013.01); H01L 21/3086 (2013.01); H01L 21/76829 (2013.01); H01L 29/0673 (2013.01); H01L 29/0847 (2013.01); H01L 29/517 (2013.01); H01L 29/6681 (2013.01); H01L 29/66545 (2013.01); H01L 29/66553 (2013.01); H01L 29/7851 (2013.01);
Abstract

A technique relates to a semiconductor device. A stack is formed over a bottom sacrificial layer, the bottom sacrificial layer being on a substrate. At least a portion of the bottom sacrificial layer is removed so as to create openings. Inner spacers are formed in the openings adjacent to the bottom sacrificial layer. The bottom sacrificial layer is removed so as to create a void. An isolation layer formed on the inner spacers so as to form an air gap, the isolation layer and the air gap being positioned between the stack and the substrate.

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