The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 11, 2020

Filed:

Jul. 29, 2019
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Wan-Ting Shih, Hsinchu, TW;

Nai-Wei Liu, Fengshan, TW;

Jing-Cheng Lin, Hsinchu, TW;

Cheng-Lin Huang, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/00 (2006.01); H01L 23/498 (2006.01); H01L 23/538 (2006.01); H01L 23/31 (2006.01); H01L 21/56 (2006.01);
U.S. Cl.
CPC ...
H01L 24/04 (2013.01); H01L 23/3114 (2013.01); H01L 23/3128 (2013.01); H01L 23/49822 (2013.01); H01L 23/5389 (2013.01); H01L 24/03 (2013.01); H01L 24/14 (2013.01); H01L 24/19 (2013.01); H01L 24/82 (2013.01); H01L 24/97 (2013.01); H01L 21/568 (2013.01); H01L 23/49816 (2013.01); H01L 24/13 (2013.01); H01L 24/32 (2013.01); H01L 24/73 (2013.01); H01L 2224/0239 (2013.01); H01L 2224/02317 (2013.01); H01L 2224/02379 (2013.01); H01L 2224/04105 (2013.01); H01L 2224/12105 (2013.01); H01L 2224/131 (2013.01); H01L 2224/13022 (2013.01); H01L 2224/13144 (2013.01); H01L 2224/13147 (2013.01); H01L 2224/13155 (2013.01); H01L 2224/24137 (2013.01); H01L 2224/32245 (2013.01); H01L 2224/73267 (2013.01); H01L 2224/97 (2013.01); H01L 2924/01022 (2013.01); H01L 2924/01029 (2013.01); H01L 2924/181 (2013.01);
Abstract

An embodiment is a method including depositing a first dielectric layer over a molding compound and a chip and patterning a first opening in the first dielectric layer to expose a contact of the chip. A first metallization layer is deposited over the first dielectric layer and in the first opening, where a portion of the first metallization layer in the first opening has a flat top. A second dielectric layer is deposited over the first metallization layer and the first dielectric layer. A second metallization layer is deposited in a second opening in the second dielectric layer, where the second metallization layer does not have a flat top within the second opening.


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