Memory system and memory cell having dense layouts

Abstract

A memory system is provided. The memory system includes a number of memory cells and a number of bit lines. The memory cells are interlocked with each other in rows and columns. The memory cells include respective capacitors, respective first transistors and respective second transistors. Respective upper plates of the respective capacitors are electrically connected to respective gates of the respective first transistors, and respective drains of the respective second transistors are connected to respective sources of the respective first transistors. The bit lines are arranged along an extending direction of the rows. Respective bit lines are connected to the respective first transistors through respective bit-line contacts, and each of the respective bit-line contacts is shared by two adjacent memory cells of the extending direction of the rows.