The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 14, 2020

Filed:

Oct. 04, 2016
Applicants:

Semiconductor Manufacturing International (Beijing) Corporation, Beijing, CN;

Semiconductor Manufacturing International (Shanghai) Corporation, Shanghai, CN;

Inventors:

Yihua Shen, Shanghai, CN;

Yunchu Yu, Shanghai, CN;

Jian Pan, Shanghai, CN;

Fenghua Fu, Shanghai, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/8234 (2006.01); H01L 27/088 (2006.01); H01L 21/84 (2006.01); H01L 21/768 (2006.01); H01L 21/8238 (2006.01); H01L 21/311 (2006.01); H01L 21/285 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0886 (2013.01); H01L 21/76897 (2013.01); H01L 21/823418 (2013.01); H01L 21/823431 (2013.01); H01L 21/823437 (2013.01); H01L 21/823475 (2013.01); H01L 21/823481 (2013.01); H01L 21/823814 (2013.01); H01L 21/823821 (2013.01); H01L 21/823871 (2013.01); H01L 21/84 (2013.01); H01L 21/845 (2013.01); H01L 21/28518 (2013.01); H01L 21/31144 (2013.01); H01L 21/76843 (2013.01); H01L 21/76855 (2013.01);
Abstract

A method for fabricating a semiconductor device includes forming a first mask layer, a second mask layer, and a plurality of first patterned layers on an interlayer dielectric layer and a plurality of gate structures. A plurality of first openings separate the first patterned layers with each across a source region, a drain region, and a portion of an isolation area between the source and the drain regions. The second mask layer is then patterned by etching. The method includes forming a plurality of discrete second patterned layers above the isolation areas between source and drain regions and then forming a patterned first mask layer by etching. Further, the method includes forming a plurality of contact vias to expose the source/drain regions through etching using the patterned first mask layer and second mask layer as an etch mask, and then forming a metal silicide layer on each source/drain region.


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