The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 07, 2020

Filed:

Jun. 28, 2019
Applicant:

Texas Instruments Incorporated, Dallas, TX (US);

Inventors:

Chang Soo Suh, Allen, TX (US);

Dong Seup Lee, McKinney, TX (US);

Jungwoo Joh, Allen, TX (US);

Naveen Tipirneni, Plano, TX (US);

Sameer Prakash Pendharkar, Allen, TX (US);

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 29/778 (2006.01); H01L 29/10 (2006.01); H01L 21/8252 (2006.01); H01L 27/06 (2006.01); H01L 27/085 (2006.01); H01L 23/535 (2006.01); H01L 29/20 (2006.01); H01L 27/07 (2006.01); H01L 27/088 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66462 (2013.01); H01L 21/8252 (2013.01); H01L 23/535 (2013.01); H01L 27/0605 (2013.01); H01L 27/085 (2013.01); H01L 29/1066 (2013.01); H01L 29/7786 (2013.01); H01L 27/0727 (2013.01); H01L 27/0883 (2013.01); H01L 29/2003 (2013.01);
Abstract

One example provides an enhancement-mode High Electron Mobility Transistor (HEMT) includes a substrate, a Group IIIA-N active layer over the substrate, a Group IIIA-N barrier layer over the active layer, and at least one isolation region through the barrier layer to provide an isolated active area having the barrier layer on the active layer. A gate stack is located between source and drain contacts to the active layer. A tunnel diode in the gate stack includes an n-GaN layer on an InGaN layer on a p-GaN layer located on the barrier layer.


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