The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 07, 2020

Filed:

Jan. 10, 2019
Applicant:

United Microelectronics Corp., Hsin-Chu, TW;

Inventors:

Chia-Hung Wang, Taichung, TW;

En-Chiuan Liou, Tainan, TW;

Chien-Hao Chen, Tainan, TW;

Jhao-Hao Lee, New Taipei, TW;

Sho-Shen Lee, New Taipei, TW;

Chih-Yu Chiang, Taoyuan, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01); H01L 21/311 (2006.01); H01L 21/768 (2006.01); H01L 21/033 (2006.01); H01L 27/108 (2006.01);
U.S. Cl.
CPC ...
H01L 21/31144 (2013.01); H01L 21/0332 (2013.01); H01L 21/0337 (2013.01); H01L 21/76802 (2013.01); H01L 27/1085 (2013.01);
Abstract

The present invention provides a method of fabricating a semiconductor pattern. Firstly, a substrate is provided, having an oxide layer thereon and a first material layer on the oxide layer, a first region and a second region are defined on the substrate. A first etching step is performed, to remove a portion of the first material layer in the first region, and then a plurality of first patterns are formed on the first material layer in the first region. A second composite layer is formed on the first pattern. Next, a second pattern layer is formed on the second composite layer in the first region, and a second etching step is performed, using the first pattern and the second pattern as a mask, to remove a portion of the second composite layer, a portion of the first material layer and a portion of the oxide layer.


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