The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 30, 2020

Filed:

Jun. 16, 2014
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Donald W. Nelson, Beaverton, OR (US);

M. Clair Webb, Aloha, OR (US);

Patrick Morrow, Portland, OR (US);

Kimin Jun, Hillsboro, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 25/065 (2006.01); H01L 23/538 (2006.01); H01L 23/00 (2006.01); H01L 21/683 (2006.01); H01L 23/498 (2006.01); H01L 25/00 (2006.01); H01L 23/427 (2006.01);
U.S. Cl.
CPC ...
H01L 25/0652 (2013.01); H01L 21/6835 (2013.01); H01L 23/49827 (2013.01); H01L 23/5389 (2013.01); H01L 24/19 (2013.01); H01L 25/0655 (2013.01); H01L 25/50 (2013.01); H01L 23/427 (2013.01); H01L 24/20 (2013.01); H01L 2221/68359 (2013.01); H01L 2223/6677 (2013.01); H01L 2224/04105 (2013.01); H01L 2224/12105 (2013.01); H01L 2224/73267 (2013.01); H01L 2924/13091 (2013.01); H01L 2924/15311 (2013.01);
Abstract

A method including forming a plurality of first devices and a plurality of first interconnects on a substrate; coupling a second device layer including a plurality of second devices to ones of the plurality of first interconnects, and forming a plurality of second interconnects on the second device layer. An apparatus including a first device layer including a plurality of first circuit devices disposed between a plurality of first interconnects and a plurality of second interconnects and a second device layer including a plurality of second devices juxtaposed and coupled to one of the plurality of first interconnects and the plurality of second interconnects, wherein one of the plurality of first devices and the plurality of second devices include devices having a higher voltage range than the other of the plurality of first devices and the plurality of second devices.


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