The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 23, 2020

Filed:

Apr. 17, 2017
Applicant:

Cypress Semiconductor Corporation, San Jose, CA (US);

Inventors:

Ching-Huang Lu, Fremont, CA (US);

Simon S. Chan, Saratoga, CA (US);

Hidehiko Shiraiwa, San Jose, CA (US);

Lei Xue, Saratoga, CA (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/26 (2006.01); H01L 27/11568 (2017.01); H01L 21/28 (2006.01); H01L 29/423 (2006.01); H01L 21/265 (2006.01); H01L 29/66 (2006.01); H01L 29/792 (2006.01); H01L 21/02 (2006.01); H01L 21/3205 (2006.01); H01L 23/528 (2006.01); H01L 23/532 (2006.01); H01L 29/51 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11568 (2013.01); H01L 21/0214 (2013.01); H01L 21/0228 (2013.01); H01L 21/02164 (2013.01); H01L 21/265 (2013.01); H01L 21/26513 (2013.01); H01L 21/32053 (2013.01); H01L 23/528 (2013.01); H01L 23/53209 (2013.01); H01L 23/53257 (2013.01); H01L 29/40117 (2019.08); H01L 29/4234 (2013.01); H01L 29/513 (2013.01); H01L 29/518 (2013.01); H01L 29/6653 (2013.01); H01L 29/66553 (2013.01); H01L 29/66833 (2013.01); H01L 29/792 (2013.01); H01L 2924/0002 (2013.01);
Abstract

An approach to use silicided bit line contacts that do not short to the underlying substrate in memory devices. The approach provides for silicide formation in the bit line contact area, using a process that benefits from being self-aligned to the oxide-nitride-oxide (ONO) nitride edges. A further benefit of the approach is that the bit line contact implant and rapid temperature anneal process can be eliminated. This approach is applicable to embedded flash, integrating high density devices and advanced logic processes.


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