The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 23, 2020

Filed:

Feb. 08, 2016
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;

Inventors:

Yao-Chun Chuang, Hsin-Chu, TW;

Yu-Chen Hsu, Hsin-Chu, TW;

Hao Chun Liu, Hsinchu, TW;

Chita Chuang, Hsin-Chu, TW;

Chen-Cheng Kuo, Chu-Pei, TW;

Chen-Shien Chen, Zhubei, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/00 (2006.01); H01L 25/00 (2006.01); H01L 21/56 (2006.01); H01L 23/31 (2006.01); H01L 25/065 (2006.01);
U.S. Cl.
CPC ...
H01L 25/50 (2013.01); H01L 21/563 (2013.01); H01L 23/3192 (2013.01); H01L 23/562 (2013.01); H01L 24/11 (2013.01); H01L 24/13 (2013.01); H01L 25/0657 (2013.01); H01L 24/16 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/05022 (2013.01); H01L 2224/05572 (2013.01); H01L 2224/10125 (2013.01); H01L 2224/13022 (2013.01); H01L 2224/13111 (2013.01); H01L 2224/13147 (2013.01); H01L 2224/14133 (2013.01); H01L 2224/14135 (2013.01); H01L 2224/16145 (2013.01); H01L 2224/73204 (2013.01); H01L 2225/06513 (2013.01); H01L 2225/06527 (2013.01); H01L 2225/06582 (2013.01); H01L 2924/00014 (2013.01);
Abstract

A method comprises depositing a protection layer over a first substrate, wherein the first substrate is part of a first semiconductor die, forming an under bump metallization structure over the protection layer, forming a connector over the under bump metallization structure, forming a first dummy plane along a first edge of a top surface of the first semiconductor die and forming a second dummy plane along a second edge of the top surface of the first semiconductor die, wherein the first dummy plane and the second dummy plane form an L-shaped region.


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