The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 23, 2020

Filed:

Feb. 27, 2019
Applicant:

Yangtze Memory Technologies Co., Ltd., Wuhan, Hubei Province, CN;

Inventors:

Jian Xu, Wuhan, CN;

Liang Xiao, Wuhan, CN;

Jin Wen Dong, Wuhan, CN;

Meng Yan, Wuhan, CN;

Li Hong Xiao, Wuhan, CN;

Assignee:

Yangtze Memory Technologies Co., Ltd., Wuhan, Hubei Province, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/4763 (2006.01); H01L 21/768 (2006.01); H01L 21/311 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76808 (2013.01); H01L 21/31144 (2013.01); H01L 21/76829 (2013.01);
Abstract

A method for forming a dual damascene interconnect structure. A substrate having a conductor layer, an etch stop layer on the conductor layer, a dielectric stack on the etch stop layer, and a hard mask layer on the dielectric stack is provided. A photoresist layer having a resist opening is formed on the hard mask layer. The hard mask layer is etched through the resist opening to form a hard mask opening. The dielectric stack is etched through the hard mask opening to form a partial via hole. The photoresist layer is trimmed to form a widened resist opening above the partial via hole. The hard mask layer is etched through the widened resist opening to form a widened hard mask opening above the partial via hole. The dielectric stack is etched through the widened hard mask opening and the partial via hole to form a dual damascene via.


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