The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 16, 2020

Filed:

Feb. 25, 2019
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Gerald Pasdast, San Jose, CA (US);

Nasser A. Kurd, Portland, OR (US);

Peipei Wang, San Jose, CA (US);

Yingyu Miao, Cupertino, CA (US);

Lakshmipriya Seshan, Santa Clara, CA (US);

Ishaan S. Shah, Santa Clara, CA (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04L 7/00 (2006.01); H03L 7/081 (2006.01); H03L 7/093 (2006.01); H03K 5/00 (2006.01); G06F 1/08 (2006.01); G06F 1/10 (2006.01); G06F 1/06 (2006.01); H03K 3/037 (2006.01);
U.S. Cl.
CPC ...
H04L 7/0008 (2013.01); G06F 1/06 (2013.01); G06F 1/08 (2013.01); G06F 1/10 (2013.01); H03K 3/037 (2013.01); H03K 5/00 (2013.01); H03L 7/0812 (2013.01); H03L 7/093 (2013.01); H03K 2005/00019 (2013.01);
Abstract

An apparatus and method is provided that compensates for the supply droops to minimize strobe shifts and to regain eye margin. The apparatus includes a droop detector to detect voltage droops at one or more trip (or threshold) levels and these detected voltage droops are translated to a shift in clock phase setting. For example, propagation delay of a delay locked loop (DLL) and/or clock edge selection from a phase interpolator (PI) is adjusted according to the detected voltage droop levels to maintain a trained relationship between the sampling clock strobe and data eye. A lookup table is used to determine a PI code or a DLL propagation delay code corresponding to a voltage droop level.


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