The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 16, 2020

Filed:

Dec. 06, 2018
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Chun-Wai Ng, Hsinchu, TW;

Hsueh-Liang Chou, Jhubei, TW;

Po-Chih Su, New Taipei, TW;

Ruey-Hsin Liu, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 29/10 (2006.01); H01L 29/06 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7809 (2013.01); H01L 29/0649 (2013.01); H01L 29/10 (2013.01); H01L 29/105 (2013.01); H01L 29/4236 (2013.01); H01L 29/66484 (2013.01); H01L 29/66666 (2013.01); H01L 29/66734 (2013.01); H01L 29/78 (2013.01); H01L 29/7813 (2013.01); H01L 29/7827 (2013.01); H01L 29/7831 (2013.01);
Abstract

A method includes forming a first semiconductor layer over a substrate, forming a second semiconductor layer over the first semiconductor layer, forming a first trench and a second trench through in the first semiconductor layer and the second semiconductor layer, wherein a width of the second trench is different from a width of the first trench, forming a dielectric region in the first trench and forming a first gate region in the first trench and over the dielectric region, and a second gate region in the second trench.


Find Patent Forward Citations

Loading…