The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 16, 2020

Filed:

Aug. 30, 2017
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Yun Lee, Taipei County, TW;

Chen-Ming Lee, Taoyuan County, TW;

Fu-Kai Yang, Hsinchu, TW;

Yi-Jyun Huang, New Taipei, TW;

Sheng-Hsiung Wang, Hsinchu County, TW;

Mei-Yun Wang, Hsin-chu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/417 (2006.01); H01L 21/768 (2006.01); H01L 29/66 (2006.01); H01L 21/3105 (2006.01); H01L 21/02 (2006.01); H01L 21/311 (2006.01); H01L 23/535 (2006.01); H01L 29/06 (2006.01); H01L 29/78 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76895 (2013.01); H01L 21/0217 (2013.01); H01L 21/31053 (2013.01); H01L 21/31111 (2013.01); H01L 21/76805 (2013.01); H01L 21/76826 (2013.01); H01L 21/76831 (2013.01); H01L 21/76832 (2013.01); H01L 23/535 (2013.01); H01L 29/0649 (2013.01); H01L 29/41791 (2013.01); H01L 29/66795 (2013.01); H01L 29/7851 (2013.01);
Abstract

A method includes providing a device structure having an isolation structure, a fin adjacent the isolation structure and taller than the isolation structure, and gate structures over the fin and the isolation structure. The isolation structure, the fin, and the gate structures define a first trench over the fin and a second trench over the isolation structure. The method further includes forming a first contact etch stop layer (CESL) over the gate structures, the fin, and the isolation structure; depositing a first inter-layer dielectric (ILD) layer over the first CESL and filling in the first and second trenches; and recessing the first ILD layer such that the first ILD layer in the first trench is removed and the first ILD layer in the second trench is recessed to a level that is about even with a top surface of the fin.


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